DRAM DESIGN ENGINEER
Descripción de la oferta de empleo
We are engaged in developing groundbreaking silicon-to-systems solutions – right from technology development and advanced memory designs to product development, systems design, and validation resulting in world-class memory solutions What's Encouraged Daily.
• Contributing to the development of new product, design flows and methodologies by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits.
• Evaluate and identify the best-known practices and communicate to all DRAM teams.
• Performing verification processes with modeling and simulation using industry-standard simulators.
Analyze results to confirm simulation to silicon correlation.
• Overseeing the layout process including floor planning, placement, and routing.
• Contributing to cross-group communication to work towards standardization and group success.
• Proactively solicit guidance from Standards, CAD, modeling, and verification groups to improve the design quality.
• Driving innovation into the future Memory generations within a dynamic work environment How To Qualify.
• BS with 3+ years' experience or MS with 2+ years' experience.
• Knowledge/experience of CMOS Circuit Design and Device Physics • Design digital or analog circuits using CMOS logic gates and transistors.
• Create floorplans that optimize for the best circuit placement, signal routing, and power delivery.
• Using Spice and Verilog, simulate to verify proper circuit operation.
Analyze circuits for power consumption, speed performance, and reliability.
• Model layout parasitics in the simulation and verify proper signal routing and power supply connections.
• Proven knowledge/experience with Verilog modeling and simulation tools • Proven knowledge/experience of state machine logic/design verification techniques Preferred Qualifications.
• Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.
• Experience in ASIC timing constraints generation and timing closure using STA tools (Primetime) and the associated design flow.
• Experience in RTL development for logic or mixed-signal circuits.
Detalles de la oferta
- Sin especificar
- Sin especificar
- 50000$ - 100000$
- 26/09/2024
- 24/12/2024
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