DIGITAL VERIFICATION METHODOLOGY LEAD
Descripción de la oferta de empleo
Micron Technology a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
As a Digital Verification Methodology Lead, you will work with a highly innovative and motivated design team using state of the art memory technologies to develop the most advanced memory products.
You will be challenged by the complexity and difficulty of verifying high density memory chips with huge scale of circuit capability, ultra-high speed designs, complex functionality which includes next Generation DDR/LPDDR and advanced low power and power management technologies.
You will need to have the ability to evaluate Full chip or block level functionality and provide solutions to help delivery of functionally correct design.
You will work closely with Micron's global design team and lead verification team members to contribute to the success of the design projects by applying verification tools and techniques, providing verification status and summaries to specific designs as needed.
Responsibilities and Duties include, but not limited to.
• Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits • Using advanced verification languages and techniques to build a cutting-edge verification platform.
• Participating in creating full chip behavior model that is distributed to Micron's world-wide external customers.
• Building a verification plan, incorporating directed and random patterns that cover all features of a memory design.
• Performing verification processes with modeling and simulation using industry standard simulators • Contributing to cross group communication to work towards standardization and group success.
• Driving innovation into the future Memory generations within a dynamic work environment Qualifications and Skills include, but not limited to.
• Fluency in verification languages (System Verilog) and methodologies (UVM) • Solid understanding of object-oriented design • Ability to abstract complex technical details into an easy-to-understand interface.
• Good debugging and problem-solving skills • Experience in using scripting language to automate tasks.
• Experience defining coverage strategy and writing coverage model.
• Must possess good communication skills and ability to work well within and lead a team.
• Previous work experience in ASIC or Memory verification • Good understanding of CMOS circuit design • Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field • 3 to 5 years' experience preferred.
Interested candidates should send their CVs through this channel.
Detalles de la oferta
- Sin especificar
- Sin especificar
- 23/08/2024
- 21/11/2024
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Modalidades: (home office), (mixta), (presencial)... manejo básiceneficios: salario competitivo $9609 pesos/mensuales/brutos... interesados comunicarse vía mensaje whatsapp con fernanda al [56] [23] [19] [75] [24]... prestaciones de ley: (seguro social, vacaciones, aguinaldo, licencia de maternidad,......
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Modalidades: (home office), (mixta), (presencial)... manejo básiceneficios: salario competitivo $9609 pesos/mensuales/brutos... interesados comunicarse vía mensaje whatsapp con fernanda al [56] [23] [19] [75] [24]... prestaciones de ley: (seguro social, vacaciones, aguinaldo, licencia de maternidad,......
Modalidades: (home office), (mixta), (presencial)... manejo básiceneficios: salario competitivo $9609 pesos/mensuales/brutos... interesados comunicarse vía mensaje whatsapp con fernanda al [56] [23] [19] [75] [24]... prestaciones de ley: (seguro social, vacaciones, aguinaldo, licencia de maternidad,......
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